Workbench · Generate
Verified Circuit Generation
Write down what the circuit must do — a histogram, a state, a unitary, and what it may use to get there. A model proposes a circuit; the simulator checks it against your spec; if it fails, the exact diagnostics go back to the model and it tries again. You get the circuit that passed, and the record of every one that did not.
1 · The spec
What this does not do. It verifies against your spec on an ideal simulator. It cannot tell whether the spec is what you meant, it ignores noise, and nothing here runs on hardware. Generation uses the same model and daily allowance as the tutor; verification runs locally and is free.
2 · Attempts
What a pass means
The verifier runs the circuit on the exact statevector simulator behind every visualization on this site and compares the result with the target you wrote. A distribution target passes when every basis state is within the tolerance. A statevector target passes when |⟨target|ψ⟩|² clears the fidelity bar; a unitary target when |Tr(V†U)|²/d² does. Both are blind to a global phase, on purpose: X and Y both prepare |1⟩ and both pass a |1⟩ spec.
A pass is a statement about the spec as written. If the spec says “50% on 00 and 50% on 11”, a circuit that prepares (|00⟩ − |11⟩)/√2 passes it — the histogram cannot see the sign. If the sign matters to you, write a statevector target.
What to watch for in the timeline
The interesting attempt is usually the second one. Read its diff: did the model change the gate the diagnostics pointed at, or something unrelated? A model that answers “|01⟩ has 100% but should have 0%” by adding a CX has read the message; one that rewrites the whole circuit has not.
Constraint failures are reported separately from physics failures. A verdict that reads “right physics, but gates outside the allowed set” means the model solved the problem and ignored the rules — the repair prompt says so in those words.
Writing a spec by hand
numQubits fixes the register width; the circuit must use exactly that many. Bitstring labels are MSB-first like Qiskit’s: qubit 0 is the rightmost character. Amplitudes and matrix entries are listed in basis order 0 … 2ⁿ−1, where index i has qubit k set when bit k of i is set; write complex entries as { "re": 0, "im": 1 }. constraints.allowedGates takes the names from the gate palette (H, X, CX, RY, …); maxDepth counts layers of gates that cannot run at the same time.
Verified on an ideal statevector simulator against the spec YOU supplied: a pass means the circuit matches that spec, not that the spec is what you meant, and says nothing about noise or real hardware.